1. Field of the Invention
The present invention relates to a nonvolatile memory, and more particularly, to a nonvolatile memory and a method for fabricating the same, which can prevent damages to a diffusion region between a selection transistor and a memory cell transistor and reduce a cell size.
2. Background of the Related Art
Being an MOS(Metal On Insulator) memory which holds information recorded in a cell even after power is cut off, the nonvolatile memory has applications in fields of power-on program storage media(for example, built in a computer bios program, various equipment set-up program and the like), operation program memories for vending machine/ticketing machine, font storage media for computer/printer and etc., game machine and the like. In general, there are MASK ROM, PROM, EPROM, EEPROM and flash EEPROM in the nonvolatile memory, and the EEPROM(Electrically Erasable and Programmable Read Only Memory) will be explained as a related art and the present invention.
A related art nonvolatile memory will be explained with reference to the attached drawings. FIG. 1 illustrates a layout of the related art nonvolatile memory, FIG. 2 illustrates a section across line I--I in FIG. 1, FIG. 3 illustrates a section across line II--II in FIG. 1, and FIG. 4 illustrates a section across line III--III in FIG. 1.
Referring to FIGS. 1.about.4, a related art EEPROM cell is provided with a semiconductor substrate 10 having an active region and a field region, which active region has a selection transistor region `A` and a cell transistor region `B` defined therein. And, there are a first and a second gate oxide films 12a and 12b form in different thicknesses on the selection transistor region `A` and the cell transistor region `B` in the semiconductor substrate 10 respectively, a selection gate line 13a formed on a region of the second gate oxide film 12a in the selection transistor region `A` in one direction, a floating gate pattern 13b and an insulating film 14 formed on a region of the second gate oxide film 12b in the cell transistor region `B` in a direction identical to the direction of the selection gate line 13a at a fixed interval, and a control gate 15a formed on the insulating film 14 in a direction identical to the direction of the floating gate pattern 13b. And, there are impurity diffusion regions 17 of a conduction type opposite to the semiconductor substrate 10 formed in the semiconductor substrate 10 on both sides of the selection gate line 13a and the floating gate pattern 13b/the control gate line 15a. The impurity diffusion regions 17 are impurity regions to be used as source and drain regions. And, there is a bit line 20 formed to cross the selection gate line 13a and the control gate line 15a. The unexplained reference numerals 18 and 21 are a first and a second interlayer insulating films, 19 is a bit line contact hole, 22 is a selection gate contact region and 23 is a common source contact region.
A related art method for fabricating the aforementioned nonvolatile memory will be explained with reference to the attached drawings. FIGS. 5a.about.5g illustrate sections across line IV--IV in FIG. 1 for showing the steps of a related art method for fabricating a nonvolatile memory.
Referring to FIG. 5a, the related art method for fabricating a nonvolatile memory starts with forming a field insulating film 11 on a field region of a semiconductor substrate 10 having a selection transistor region `A`, a cell transistor region `B` and the field region defined thereon. Then, a first and a second gate oxide films 12a and 12b with thicknesses different from each other are formed on the selection transistor region `A` and the cell transistor region `B", respectively. The first gate oxide film 12a on the selection transistor region `A` is thicker than the second gate oxide film 12b on the cell transistor region `B`. The thin second gate oxide film 12b on the cell transistor region `B` is a tunneling oxide film. As shown in FIG. 5b, a first polysilicon layer is deposited on an entire surface, and the first polysilicon layer on regions of the first and second gate oxide films 12a and 12b in the selection transistor region `A` and the cell transistor region `B` are subjected to selective patterning (photolithography+etching), to form a selection gate line 13a on the selection transistor region `A` and a floating gate pattern 13b on the cell transistor region `B`. Then, an insulating film 14 is formed on entire surfaces of the first and second gate oxide films 12a and 12b including the selection gate line 13a and the floating gate pattern 13b. The insulating film 14 is of an ONO(Oxide Nitride Oxide) structure. Though not shown in the drawings, the floating gate pattern 13b, patterned in a horizontal direction, is separated in a rectangular form. As shown in FIG. 5c, a second polysilicon layer 15 is formed on an entire surface of the insulating film 14. As shown in FIG. 5d, a first photoresist film PR1 is coated on the second polysilicon layer 15 and subjected to selective patterning by exposure and development, to remove the first photoresist film PR1 from upper portions of the selection transistor region `A` and the cell transistor region `B` adjacent to tie selection transistor region `A`. The patterned first photoresist film PR1 is used as a mask to remove the second polysilicon layer 15 selectively, only to leave the second polysilicon layer 15 on the insulating film 14 on the cell transistor region `B`. If the second polysilicon layer 15 is left only on a region on which the control gate line is to be formed for forming the control gate line, because the selection gate line 13a is also etched as the floating gate pattern 13b under the control gate line is etched, only the second polysilicon layer 15 on the selection transistor region `A` is removed at first. Then, as shown in FIG. 5e, the first photoresist film PR1 is removed, and a second photoresist film PR2 is coated on the second polysilicon layer 15 including the insulating film 14, and subjected to patterning by exposure and development, to leave one portion of the second photoresist film PR2 on an entire surface of the selection transistor region `A` and the other portion on the second polysilicon layer 15 over the floating gate pattern 13b on the cell transistor region `B` spaced from the one portion. The patterned second photoresist film PR2 is used as a mask in selectively etching and removing the second polysilicon layer 15 and the floating gate pattern 13b, to form a control gate line 15a. Upon etching the second polysilicon layer 15 and the floating gate pattern 13b of the first polysilicon layer, the semiconductor substrate 10 not masked by the second photoresist film PR2 at an interface of the selection transistor region `A` and the cell transistor region `B` is also etched, to form a trench 16, because of etch selectivities and etch rates. In general, though an oxide film, a nitride film and a polysilicon layer differ in the etch selectivities, an etching time period should be paid attention because an oxide film and a nitride film are etched to some extents in a condition a polysilicon layer is etched. And, under the same etch condition, an etch rate of the nitride film is higher than the polysilicon layer, and an etch rate of the oxide film is higher than the nitride film. Because of these reasons, when the second polysilicon layer 15 and the floating gate pattern 13b are etched, the ONO structured insulating film 14 and the thin second gate oxide film 12b are also etched as well as the semiconductor substrate 10, forming the unnecessary trench 16. As shown in FIG. 5f, the second photoresist film PR2 is removed, and the selection gate line 13a and the control gate line 15a are used as a mask in conducting an ion injection to form impurity regions 17 in the semiconductor substrate 10 on both sides of the selection gate line 13a and the control gate line 15a. Then, a first interlayer insulating film 18 is deposited on an entire surface of the semiconductor substrate 10 including the selection gate line 13a and the control gate line 15a, a bit line contact region is defined therein, and the first interlayer insulating film 18, the insulating film 14 and the first gate oxide film 12a, all of which are in the bit line contact region, are subjected to selective patterning(photolithography+etching), to form a bit line contact hole 19. Then, a bit line 20 is formed on an entire surface of the first interlayer insulating film 18 including the bit line contact hole 19 and subjected to patterning to a fixed width. As shown in FIG. 5g, a second interlayer insulating film 21 is deposited on the first interlayer insulating film 18 including the bit line 20. In addition to this, a signal application region to the selection gate line 13a is defined at one side of the bit line 20(see FIG. 1), and the first and second interlayer insulating films 18 and 21 over the selection gate line 13a are selectively removed to form a selection gate contact hole 22. And, a common source contact region 23 is formed in an N.sub.+ diffusion region in the cell transistor legion `B`.
However, the related art nonvolatile memory and method for fabricating the same have the following problems.
The formation of unnecessary trench in the semiconductor substrate between the selection transistor region and the cell transistor region leads to form irregular impurity regions, that drops a device reliability.